Semiconductor devices are used in many electronic applications, such as radios, televisions, cell phones and computers, as examples. Semiconductor devices are often fabricated as integrated circuits, with hundreds or thousands of devices often being manufactured on a single chip.
After a semiconductor device or integrated circuit has been fabricated, electrical connections must be made to the semiconductor device in order to connect it to other electronic components. This is usually accomplished by, after attaching the device to a package substrate or lead frame, making electrical connection between the bond pads of the device and the inner leads of the package, and the package leads are connected to pins located on the exterior of the package. Wire bonding is a common technique for making connections between the semiconductor device inputs/outputs (I/O's) and the package, especially for integrated circuits having up to about 224 I/O's.
Wire bonding is typically carried out after the integrated circuit is attached to a package. Flexible wires are usually attached one at a time to bond pads on the integrated circuit, and the other end of the flexible wire is attached to a contact on the package. Three types of wire bond methods include thermocompression bonding, ultrasonic bonding, and thermosonic bonding, as examples.
In order facilitate the wire bonding process, typically an integrated circuit 100 will have bond pads 112 formed at a top surface thereof, as shown in the prior art drawing of FIG. 1. In the semiconductor device 100 shown, a workpiece 102 having an insulating layer 104 formed at a top region thereof has a conductive region 106 or a plurality of conductive regions 106 formed within the insulating layer 104. The conductive regions 106 may comprise conductive lines, or may alternatively comprise a pad of conductive material formed in a circular or square shape, as examples. The conductive regions 106 may be electrically coupled to circuits or elements (not shown) that have been formed in the underlying workpiece 102, for example.
To form a bond pad 112, typically a passivation layer 108 is deposited over the insulating layer 104 and exposed portions of the conductive regions 106. The passivation layer 108 typically comprises a first layer comprised of plasma enhanced silicon nitride (PE-SiN) deposited in a thickness of about 0.075 μm. The passivation layer also includes a second layer of plasma enhanced silicon dioxide (PE-OX) deposited in a thickness of about 0.4 μm over the first PE-SiN layer. The passivation layer 108 also includes a third layer of PE-SiN deposited in a thickness of about 0.6 μm over the PE-OX layer.
The passivation layer 108 is patterned to expose a portion of the top surface of the conductive regions 106 using traditional photolithography and a photoresist (not shown), and a bond pad material 112 is deposited over the patterned passivation layer 108. The bond pad material 112 may conform to the underlying topography of the underlying patterned passivation layer 108, as shown. The bond pad material 112 is then patterned, also using traditional photolithography techniques and a photoresist (not shown), to form bond pads 112 that are electrically coupled to the underlying conductive regions 106. Wires may then be bonded to the bond pads 112 to electrically connect the semiconductor device 100 to a package or another semiconductor device or circuit, for example.
There is a trend in the semiconductor industry towards scaling or reducing the size of integrated circuits. As a result, the minimum feature size of integrated circuits is becoming smaller and smaller. This makes the wire bonding process for semiconductor devices more challenging. For example, as shown in FIG. 1, the space “x” between adjacent bond pads 112 may be 3 μm or less. After a wire 114 is bonded to the bond pads 112, as shown in FIG. 2, shorts 116 may be formed between adjacent bond pads 112 due to the deformation and distortion of the bond pads 112 during the wire bonding process.
Therefore, what is needed in the art is a bond pad scheme that prevents electrical shorts between adjacent bond pads when the semiconductor device is subjected to mechanical stress, such as wire bonding.